A project highlighted on August 7, 2026, turns conventional processor optimization upside down by seeking the longest possible latency for a single assembly instruction. The open-source “Assembly Hall of Shame” documents techniques that make instructions unusually slow on particular Intel, AMD and VIA systems.
The leaderboard begins with `nop`, an instruction that performs no operation, then explores increasingly elaborate ways to delay retirement. Entries target microcode assists, cache and translation lookaside buffer behaviour, model-specific registers, I/O ports and memory-mapped devices. Results are hardware-specific experiments rather than claims about ordinary application performance.
One strategy supplies division instructions with operands selected to take long internal paths. Another uses denormal floating-point values that hand processing to microcode. A lock-prefixed operation is aligned across a cache-line boundary to force an external bus lock instead of the faster cache-coherence route. Other entries fill write-combining buffers before an `mfence` or dirty cache lines before an invalidation operation.
The most extreme approach described uses `fxrstor64`, which loads 512 bytes of floating-point and vector state, from a high-latency memory-mapped I/O region on the PCIe fabric. At the same time, other processor cores repeatedly read another slow device register. Those non-posted transactions congest the root complex and endpoint, leaving the state load queued behind competing traffic.
Hardware peripherals become part of the experiment. Researchers search unused PCIe address space for slow GPU registers, target an I/O location spanning a network-card register boundary, and probe an ACPI power-management block with an unaligned read. Some operations are outside architectural specifications or touch unknown registers, making them unsuitable for normal systems.
The repository lists an Intel Core i7-8559U and AMD Ryzen 7 5800H among tested processors. It also notes an undocumented VIA model-specific register with high response time. These observations do not establish the same latency on other chips, firmware versions, boards or attached devices.
The project overlaps with security research because pathological instruction behaviour can expose hidden microarchitectural paths. It references a prior experiment in which an unaligned vector load from stalled GPU registers disrupted assumptions underlying System Management Mode. Even so, this repository is framed as a race to the performance floor, not a general vulnerability advisory.
Reproducing such tests carries risk. Unknown MMIO locations, privileged registers, bus locks and deliberately saturated hardware can freeze or destabilize a machine. The supplied documentation does not present the techniques as safe benchmarks for production computers.
As a research exercise, the Hall of Shame makes an unusual point about performance: instruction names do not determine latency by themselves. Operands, alignment, microcode, privilege, cache state and connected devices can dominate execution time. By maximizing those effects rather than minimizing them, the project maps obscure boundaries in modern CPU and platform behaviour.
